1. Technical Field
The present invention relates to a liquid crystal display panel of a horizontal electric field-type such as a fringe field switching (hereinafter, referred to as “FFS”) mode, and more particularly, to a horizontal electric field-type liquid crystal display panel having a unit for preventing burn-in due to a voltage applied to scanning lines.
2. Related Art
As liquid crystal display panels, although liquid crystal display panels of a vertical electric field-type such as a TN (twisted nematic) mode, a VA (vertical alignment) mode, or an MVA (multi-domain vertical alignment) mode are widely used, horizontal electric field-type liquid crystal display panels in which electrodes are included in one substrate only are also known. Among the horizontal electric field-type liquid crystal display panels, the operating principle of a liquid crystal display panel of an IPS (in-plane switching) mode will be described with reference to FIGS. 9 to 11 (see JP-A-10-319371 (Paragraphs [0005], [0053], and [0065] to [0077], and FIGS. 2, 5, and 6) and JP-A-2002-131767 (Claims, Paragraphs [0006] to [0009], and [0018] to [0077], and FIGS. 1 and 3)).
FIG. 9 is a schematic plan view of one pixel of a general liquid crystal display panel of the IPS mode as an example. FIG. 10 is a cross-sectional view of FIG. 9 taken along line X-X. FIG. 11 is a cross-sectional view of FIG. 9 taken along line XI-XI.
The liquid crystal display panel 50 of the IPS mode includes an array substrate AR and a color filter substrate CF. In the array substrate AR, a plurality of scanning lines 52 and common wirings 53 are disposed to be parallel to the surface of a first transparent substrate 51. In addition, a plurality of signal lines 54 are disposed in a direction for intersecting the scan lines 52 and the common wiring 53. In a center portion of each pixel, an opposing electrode (also referred to as a common electrode) 55, for example, having a comb shape as shown in FIG. 9 is disposed in a strip shape extending from the common wiring 53, and a comb-shaped pixel electrode 56 is disposed so as to interpose peripherals of the opposing electrode 55 therebetween. The surfaces of the opposing electrode 55 and the pixel electrode 56 are coated with a protection insulation film 57, for example, formed of silicon nitride and an alignment film 58 formed of polyimide or the like.
In addition, around intersections between the scanning lines 52 and the signal lines 54, TFTs (thin film transistors) as switching elements are formed. In the TFT, a semiconductor layer 59 is disposed between the scanning line 52 and the signal line 54, a signal line portion on the semiconductor layer 59 forms a source electrode S of the TFT, a scanning line 12 portion of the lower part of the semiconductor layer 59 forms a gate electrode G, and a conductive layer that is overlapped with a part of the semiconductor layer 59 forms a drain electrode D, and the drain electrode D is connected to the pixel electrode 56.
The color filter substrate CF has a configuration in which a color filter layer 61, an overcoat layer 62, and an alignment film 63 are disposed on the surface of a second transparent substrate 60. The array substrate AR and the color filter substrate CF are disposed to face each other such that the pixel electrode 56 and the opposing electrode 55 of the array substrate AR and the color filter layer 61 side of the color filter substrate CF are disposed so as to face each other. Next, a liquid crystal LC is sealed between the array substrate AR and the color filter substrate CF, and polarizing plates 64 and 65 are disposed on outer sides of both the substrates such that polarizing directions thereof intersect each other, and thereby the IPS-mode liquid crystal display panel 50 is formed.
In the IPS-mode liquid crystal display panel 50, as shown in FIGS. 10 and 11, when an electric field is formed between the pixel electrode 56 and the opposing electrode 55, the liquid crystal that has been aligned horizontally rotates in a horizontal direction, whereby the amount of transmission of light incident from a back light can be controlled. Although the IPS-mode liquid crystal display panel 50 has advantages that it has a wide viewing angle and high contrast, the opposing electrode 55 is formed of a same metal material as those of the common wiring 53 and the scanning line 52, and accordingly, there are problems that the liquid crystal display panel has a low aperture ratio and low transmittance and has a change in a display color depending on the viewing angle.
In order to solve the problems of the low aperture ratio and low transmittance in the above-described IPS-mode liquid crystal display panel, FFS-mode liquid crystal display panels have been developed (see JP-A-2002-14363 (Claims, Paragraphs [0002] to [0010] and [0019] to [0026], and FIGS. 1 and 2) and JP-A-2002-244158 (Claims, Paragraphs [0002] to [0013] and [0023] to [0032] and FIGS. 1 to 4)). The operating principle of the FFS-mode liquid crystal display panel will be described with reference to FIGS. 12 to 15.
FIG. 12 is a schematic plan view of one pixel of a general liquid crystal display panel of the FFS mode as an example. FIG. 13 is a cross-sectional view of FIG. 12 taken along line XIII-XIII. FIG. 14 is a cross-sectional view of FIG. 12 taken along line XIV-XIV. FIG. 15 is a schematic plan view of one pixel of an FFS-mode liquid crystal display panel having a structure in which slits of pixel electrodes are tilted.
The liquid crystal display panel 70A of the FFS mode includes an array substrate AR and a color filter substrate CF. In the array substrate AR, a plurality of scanning lines 72 and common wirings 73 are disposed to be parallel to the surface of a first transparent substrate 71. In addition, a plurality of signal lines 74 are disposed in a direction for intersecting the scan lines 72 and the common wiring 73. In addition, a common electrode (also referred to as an opposing electrode) 75 formed of a transparent material including ITO (indium tin oxide), IZO (indium zinc oxide), or the like which is connected to the common wiring 73 for covering areas partitioned by the scanning lines 72 and the signal lines 74 is disposed. In addition, pixel electrodes 78A formed of a transparent material such as ITO in which a plurality of slits 77A in the shape of stripes is formed are disposed on the surface of the common electrode 75 through an insulation film 76. The surfaces of the pixel electrodes 78A and a plurality of slit 77A portions are coated with an alignment film 80.
In addition, around intersections between the scanning lines 72 and the signal lines 74, TFTs (thin film transistors) as switching elements are formed. In the TFT, a semiconductor layer 79 is disposed on the surface of the scanning line 72, a part of the signal line 74 extends so as to cover a part of the surface of the semiconductor layer 79, and thereby a source electrode S is formed. In addition, a scanning line portion of the lower part of the semiconductor layer 79 forms a gate electrode G, and a conductive layer that is overlapped with a part of the semiconductor layer 79 forms a drain electrode D. The drain electrode D is connected to the pixel electrode 78A.
The color filter substrate CF has a configuration in which a color filter layer 83, an overcoat layer 84, and an alignment film 85 are disposed on the surface of a second transparent substrate 82. The array substrate AR and the color filter substrate CF are disposed to face each other such that the pixel electrode 78A and the common electrode 75 of the array substrate AR and the color filter layer 83 of the color filter substrate CF are disposed so as to face each other. Next, a liquid crystal LC is sealed between the array substrate AR and the color filter substrate, and polarizing plates 86 and 87 are disposed on outer sides of both the substrates such that polarizing directions thereof are perpendicular to each other, and thereby the FFS-mode liquid crystal display panel 70A is formed.
In the FFS-mode liquid crystal display panel 70A, when an electric field is formed between the pixel electrode 78A and the common electrode 75, as shown in FIGS. 13 and 14, the electric field is in a direction toward the common electrode 75 from both sides of the pixel electrode 78A. Accordingly, not only liquid crystal molecules in the slits 77A, but also liquid crystal molecules on the pixel electrode 78A can be moved. Since the FFS-mode liquid crystal display panel 70A has a wider viewing angle, higher contrast, and higher transmittance than the IPS-mode liquid crystal display panel 50, bright display can be achieved. In addition, since the FFS-mode liquid crystal display panel 70A has an overlapped area between the pixel electrode 78A and the common electrode 75 in a plan view larger than that of the IPS mode liquid crystal display panel 50, a larger holding capacitance is secondarily formed, and accordingly, there is an additional advantage that an additional auxiliary capacitance line is not needed to be disposed in the FFS-mode liquid crystal display panel 70A.
In the FFS-mode liquid crystal display panel, it is preferable that the rubbing direction is perpendicular to the signal line and the pixel electrode and the rubbing direction forms a tilt of a minute angle, in consideration of the display characteristic thereof. Accordingly, as in the FFS-mode liquid crystal display panel 70B shown in FIG. 15, a configuration in which the slits 77B having a stripe shape disposed in the pixel electrode 78B are tilted with respect to the scanning line 72 and the common wiring 73 is used. In addition, since the only difference between the FFS-mode liquid crystal display panel 70B shown in FIG. 15 and the FFS-mode liquid crystal display panel 70A shown in FIG. 12 is the tilted angle of the slits 77B disposed in the pixel electrode 78B, a same reference numeral is assigned to a constituent part that is the same as that of the FFS-mode liquid crystal display panel 70A shown in FIG. 12, and a detailed description thereof is omitted here.
As described above, since the FFS-mode liquid crystal display panel has a wider viewing angle, higher contrast, and higher transmittance than the IPS-mode liquid crystal display panel, bright display can be achieved. In addition, the FFS-mode liquid crystal display panel can be driven at a low voltage level and can have an excellent display quality without disposing an additional capacitance line owing to secondary formation of large holding capacitance.
However, it is known that a burn-in phenomenon occurs in a case where a liquid crystal display panel is used for a long time. Such a burn-in phenomenon occurs in both the IPS-mode liquid crystal display panel and the FFS-mode liquid crystal display panel. However, it has been found that the burn-in phenomenon occurs more severely in the above-described general FFS-mode liquid crystal display panel than the general IPS-mode liquid crystal display panel. According to various experiments performed by inventors, the difference between the degrees of the burn-in phenomena in the FFS-mode and the IPS-mode is estimated to be caused by asymmetry of the path of electric flux lines from the pixel electrode toward the liquid crystal and the path of electric flux lines from the liquid crystal toward the scanning line in the FFS-mode liquid crystal display panel while the paths of the electric flux lines are symmetrical to each other in the IPS-mode liquid crystal display panel.
In other words, in the IPS-mode liquid crystal display panel and the FFS-mode liquid crystal display panel, a voltage level applied to the scanning line in a non-section state of a specific pixel is, for example, about −10 V, and a voltage level applied to the scanning line in a selection state of a specific pixel is about +15 V. However, since a period during which a specific pixel is selected is very short, a DC voltage of about −10 V is applied to the scanning line for a long time. In addition, in the IPS-mode liquid crystal display panel, as clearly shown in FIG. 11, the electric flux lines E1 from the pixel electrode 56 toward the scanning line 52 enter into the liquid crystal layer LC through the pixel electrode 56, the protection insulation film 57, and the alignment film 58, and reach the scanning line 52 through the alignment film 58 and the protection insulation film 57 from the liquid crystal layer LC. In other words, in the IPS-mode liquid crystal display panel, the path of the electric flux lines from the pixel electrode 56 to the liquid crystal layer LC and the path of the electric flux lines from the liquid crystal layer LC to the scanning line 52 are symmetrical to each other.
On the other hand, in the FFS-mode liquid crystal display panel, as clearly shown in FIG. 14, the electric flux lines E2 from the pixel electrode 78A toward the scanning line 72 enter into the liquid crystal layer LC through the alignment film 80 from the pixel electrode 78A, and reach the scanning line 72 though the alignment film 80 and the insulation film 76 from the liquid crystal layer LC. In other words, in the FFS-mode liquid crystal display panel, the path of the electric flux lines from the pixel electrode 78A to the liquid crystal layer LC and the path of the electric flux lines from the liquid crystal layer LC to the scanning line 72 are asymmetrical to each other. Accordingly, in the FFS-mode liquid crystal display panel, the pixel electrode 78A and the alignment film 80 disposed on the surface thereof are easily influenced by a DC electric field due to a signal applied to the scanning line 72 irreversibly more than in the IPS-mode liquid crystal display panel, and it is estimated to cause the severe burn-in phenomenon.
It is difficult to configure the path of electric flux lines from the pixel electrode to the liquid crystal layer and the path of electric flux lines from the liquid crystal layer to the scanning line symmetrical to each other for reducing the burn-in problem of the above-described FFS-mode liquid crystal display panel, when the operating principle of the FFS-mode liquid crystal display panel is considered. However, inventors have found a method of reducing the burn-in phenomenon of the FFS-mode liquid crystal display panel by preventing application of the DC electric field on the basis of a high-voltage signal applied to the scanning line to liquid crystals nearby, and the invention has been accomplished.
In addition, in JP-A-2002-131767, in the IPS-mode liquid crystal display panel, an example in which a conduction layer partially overlapped with one between the signal line and the scanning line is disposed for preventing light leakage due to a liquid crystal driven by an electric field generated between the signal line (drain signal line) or the scanning line (gate signal line) and an adjacently disposed electrode is disclosed. In addition, a description partially implying an FFS-mode liquid crystal display panel is made therein (see Paragraphs [0003] to [0004]). However, in JP-A-2002-131767, a detailed example of the FFS-mode liquid crystal display panel is not described, and there is no description for implying the problem of burn-in in the IPS-mode liquid crystal display panel and the FFS-mode liquid crystal display panel.